Optimization of Schematic Tiling Technique using Cadence SKILL Code

Abstract

As the world is digitizing, requisite of memory rising exponentially. The time to deliver memory is the requirement of today’s world. But to design and analyze the performance of a memory is a time-consuming process. The schematic design needs to be speed up. The Tiler code is a probable solution to optimize the design process. It uses SKILL script language of Cadence Virtuoso to design symbol and schematic of a G level of a memory. It reduces tremendous amount of time and goofy errors. This paper presents the tiling technique to design memory’s G level schematic and symbol.