Improving Robustness of Dual Port SRAM by finding additional bugs in design using ESPCV flow to compare Schematics v/s Verilog on 12LP GF Technology as an example

Abstract

 Robustness in design is one of the major concerns in memory design, this will be checked with the help of various verification techniques used in the industry. Functional verification is used to check whether the design meets the specification. Evolution in verification has led to the development of formal verification tools nowadays. The symbolic simulators involve the formal verification technique along with the simulation approach. This makes debugging of circuit faults easier. ESP-CV is a symbolic simulator designed for functional verification and sequential equivalence checking of custom memory design. Symbolic simulation compares two design i.e. behavioral RTL verilog and transistor-level SPICE netlist by generating testbenches for different cycles. This article includes the basic flow of ESP-CV simulation and how this flow helps in improving robustness of SRAM design. This tool is used early in the design flow because of its ability to read RTL models and Spice netlists directly. This article also diagrams the key difficulties of memory check, and proceeds to depict how symbolic simulation and its basic advancements offer points of interest for confirming full-custom circuit design