Design of Pulse-Triggered Flip-Flop

Abstract

- Low Power Flip-Flop design involves pulse triggered clock generation mechanism, in which explicit pulse triggering has several advantages. Among all detailed design methods, signal feed-through pulse triggered flip-flop is most effective in all design aspects, i.e., speed area and delay. In this paper, further modification of this design is suggested, along with FinFET based design is carried out, which further reduces the power dissipation inside the chip and optimizes PDP. All of the inventions are carried out using TSMC 30-nm design technology. HSPICE simulation software is used for waveform generation and power, timing parameter calculations